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Cache Simulator
Processor Simulator
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Memory Access
Address
Cache
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RAM SIZE:
32 MB
>
16 MB
8 MB
4 MB
CACHE SIZE:
16 KB
8 KB
4 KB
BLOCK SIZE:
512 B
256 B
128 B
64 B
METHOD:
Direct mapped
Fully Associative
Set Associative
Set:
8 Blocks
4 Blocks
2 Blocks
Algorithm:
LRU
FIFO
Random
Addresses in input
Format: hex addresses (fitting into the chosen RAM), one per line
Generate Random
or